1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method for manufacturing the same, which are suitable for efficient layout design and cell size reduction.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., ferroelectric random access memory (FRAM) has data processing speed as much as dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a net generation memory device.
The FRAM and DRAM are memory devices which have almost similar structures, and include a ferroelectric capacitor having high residual polarization characteristic. Such residual polarization characteristic permits data not to be erased even if electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric.
As shown in FIG. 1, even if polarization organized by electric field removes electric field, data is maintained at a certain amount (d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is applied as a memory device by corresponding d, a state to 1, 0, respectively.
A driving circuit of a related art nonvolatile ferroelectric memory device will be described with reference to the accompanying drawings.
FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 whose gate is connected with the wordline and source is connected with the bitline, and a ferroelectric capacitor FC1 whose first terminal is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
Data input/output operation of the related art nonvolatile ferroelectric memory device will be described below.
FIG. 3a is a timing chart illustrating the operation of write mode of the related art nonvolatile ferroelectric memory device and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
In case of write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts.
Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state, so that cell is selected.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is high.
To write a logic value "1" or "0" in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bit line.
In other words, a high signal is applied to the bitline, and if the signal applied to the plate line in a period, where the signal applied to the wordline is high, is low, a logic value "1" is written in the ferroelectric capacitor.
A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value "0" is written in the ferroelectric capacitor.
Reading operation of data stored in a cell by the above operation of the write mode will be described below.
If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal before a corresponding wordline is selected.
Then, the respective bitline becomes inert and address is decoded. The low signal is transited to the high signal in the corresponding wordline by the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destruct data corresponding to the logic value "1" stored in the ferroelectric memory.
If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destructed.
The destructed data and the data which is not destructed are output as different values by the aforementioned hysteresis loop principle, so that a sensing amplifier senses the logic value "1" or "0".
In other words, if the data is destructed, "d" state is transited to "f" state as shown in hysteresis loop of FIG. 1. If the data is not destructed, "a" state is transited to "f" state. Thus, if the sensing amplifier is enabled after a certain time has elapsed, the logic value "1" is output in case that the data is destructed while the logic value "0" is output in case that the data is not destructed.
As aforementioned, after the sensing amplifier outputs data, to recover the data to original data, the plate line becomes inert from high state to low state at the state that high signal is applied to the corresponding wordline.
The structure of the aforementioned related art nonvolatile ferroelectric memory device and a method for manufacturing the same will be described.
FIG. 4a is a layout of the related art nonvolatile ferroelectric memory device.
As shown in FIG. 4a, the related art nonvolatile ferroelectric memory device includes a first active region 41 and a second active region 41a which are asymmetrically formed spaced apart from each other, a second wordline W/L1 formed across the first active region 41, a second wordline W/L2 formed across the second active region 41a and spaced apart from the first wordline W/L1, a first bitline B/L1 formed across the first and second wordlines at one side of the first active region 41, a second bitline B/L2 formed across the first and second wordlines at one side of the second active region 41a, a first ferroelectric capacitor FC1 electrically connected with the first active region and formed over the first and second wordlines W/L1 and W/L2, a second ferroelectric capacitor FC2 electrically connected with the second active region 41a and formed over the first and second wordlines W/L1 and W/L2, a first plate line P/L1 electrically connected with the first ferroelectric capacitor FC1 and formed on the first wordline W/L1, and a second plate line P/L2 electrically connected with the second ferroelectric capacitor FC2 and formed on the second wordline W/L2.
FIG. 4a is a layout of the related art nonvolatile ferroelectric memory device based on unit cell. In such a related art nonvolatile ferroelectric memory device, the first and second capacitors FC1 and FC2 are formed along the bitline, the first plate line P/L1 is formed on the first wordline W/L1,and the second plate line P/L2 is formed on the second wordline W/L2.
The aforementioned related art nonvolatile ferroelectric memory device will be described in detail with reference to FIG. 4b.
FIG. 4b is a sectional view illustrating a related art nonvolatile ferroelectric memory device taken along line I-I' of FIG. 4a.
As shown in FIG. 4b, the related art nonvolatile ferroelectric memory device includes a substrate 51 in which an active region and a field region are defined, a first wordline 54 and a second wordline 54a which are formed on a first insulating layer 53 on the active region and the field region, first source/drain impurity regions 55 and 56 formed at both sides of the first wordline 54, second source/drain impurity regions (not shown) formed at both sides of the second wordline 54a, a second insulating layer 57 formed on an entire surface including the first and second wordlines 54 and 54a, having a contact hole to expose the first drain impurity region 56, a first plug layer 58a buried in the contact hole, a first metal layer 59 for connecting the first plug layer 58a with a first bitline(not shown), a third insulating layer 60 formed on the entire surface including the first metal layer 59, having a contact hole to expose the first source impurity region 55, a second plug layer 62 buried in the contact hole, a barrier metal layer 63 electrically connected with the second plug layer 62 and formed over the first wordline 54 and the second wordline 54a, a lower electrode 64 of the first ferroelectric capacitor FC1 formed on the barrier metal layer 63, a ferroelectric film 65 and an upper electrode 66 of the second ferroelectric capacitor which are sequentially deposited on the lower electrode 64 of the first ferroelectric capacitor, a fourth insulating layer 67 formed on the entire surface including the upper electrode 66 of the second ferroelectric capacitor, a first plate line 68 electrically connected with the upper electrode 66 of the first ferroelectric capacitor FC1 through the fourth insulating layer 67 and formed in a position corresponding to an upper side of the first wordline 54, and a second plate line 68a formed in a position corresponding to an upper side of the second wordline 54a and spaced apart from the first plate line 68.
The method for manufacturing the aforementioned related art nonvolatile ferroelectric memory device will be described with reference to FIGS. 5a to 5d.
FIGS. 5a to 5d are sectional views illustrating the method for manufacturing the related art nonvolatile ferroelectric memory device, taken along line I-I' of FIG. 4a.
As shown in FIG. 5a, the semiconductor substrate 51 is partially etched to form a trench and then an insulating layer is buried in the trench to form a device isolation layer 52.
A first insulating layer 53 is formed on a substrate 51 of an active region including the device isolation layer 52. A wordline material layer is formed on the first insulating layer 53 and then patterned to form first and second wordlines 54 and 54a spaced apart from each other.
As shown in FIG. 5b, source and drain impurity regions 55 and 56 having conductivity type opposite to the substrate 51 are formed by impurity ion implantation using the wordlines 54 and 54a as masks.
The source/drain impurity regions 55 and 56 are source/drain impurity regions of a first transistor Ti which uses the first wordline 54 as a gate electrode.
Afterwards, a second insulating layer 55 is formed on an entire surface of the substrate 51 including the first and second wordlines 54 and 54a. A photoresist(not shown) is then deposited on the second insulating layer 55 and then patterned. The second insulating layer 55 is selectively removed by etching process using the patterned photoresist as a mask to expose the drain impurity region 56 so that a contact hole 58 is formed.
As shown in FIG. 5c, a conductive material is buried in the contact hole to form a first plug layer 58a, and a first metal layer 59 for connecting the first plug layer 58a with the first bitline B/L1 is formed. At this time, the second bitline B/L2 is electrically connected with the drain impurity region of a second transistor T2 (not shown).
Subsequently, as shown in FIG. 5d, a third insulating layer 60 is formed on the entire surface including the first metal layer 59. A photoresist(not shown) is deposited on the third insulating layer 60 and then patterned. The third insulating layer 60 is selectively removed by etching process using the patterned photoresist as a mask to expose the source impurity region 55 so that a contact hole 61 is formed.
As shown in FIG. 5e, the conductive material is buried in the contact hole 61 to form a second plug layer 62 electrically connected with the source impurity region 55.
A barrier metal layer 63 is then formed to be electrically connected with the second plug layer 62. A lower electrode 64 of a first ferroelectric capacitor FC1, a ferroelectric film 65, and an upper electrode 66 of the first ferroelectric capacitor are sequentially formed on the barrier metal layer 63.
As shown in FIG. 5f, a fourth insulating layer 67 is formed on the upper electrode 66 of the first ferroelectric capacitor. The fourth insulating layer 67 is then selectively etched by photolithography process to partially expose the upper electrode 66 of the first ferroelectric capacitor so that a contact hole is formed. Finally, a first plate line 68 electrically connected with the upper electrode 66 of the first ferroelectric capacitor through the contact hole is formed. As a result, the method for manufacturing the related art nonvolatile ferroelectric memory device is completed. A reference numeral "68a" which is not described denotes a second plate line.
However, the related art nonvolatile ferroelectric memory device and the method for manufacturing the same have several problems.
To ensure the capacitance, the lower electrode of the capacitor requires a thick thickness. However, in case that the lower electrode of the capacitor is too thickly formed, it is difficult to etch the lower electrode of the capacitor made of metal material. For this reason, there is limitation to ensure the capacitance.
In addition, since the wordline and the plate line are formed in unit cell, a space for forming the plate line is not ensured sufficiently, in which the wordline of an adjacent cell and the plate line are separated from each other. Therefore, since the plate line is formed in such a narrow space, difficult process steps are caused.